Toshiba TLCS-900/H1 Series Manual page 365

LCDCCR0 Bit symbol
(0288H)
Read/Write
Reset State
Function
Delay control 1 is set by LCDCCR0<PCPV2:0>. Delay of Dummy clock is controlled
by pulse number derived by subtracting common number and <PCPV2:0> from
LCDFFP<FP9:0> (refer to SR mode section).
LCDCCR1 Bit symbol
(0289H)
Read/Write
Reset State
Function
Set up time of LLP (horizontal front porch) is set in LCDCCR1<TLDE4:0>. This is
called "Delay control 2". 1 pulse of this set up time in LCDCCR1 register is equal to 8
times of fsys regardless of LCP0 and LCP1. The set up time has offset time; fsys*14 to
16(f
delayed. This offset time changes according to the setting conditions. The cycle of
LCP1 is determined by (the value of LCDSCC register +1) * fsys * 16, thus horizontal
back porch is the time when offset time and set up time are subtracted from the cycle
of LCP1.
LCDCCR2 Bit symbol LLPSU7
(028AH)
Read/Write
Reset State
Function
The pulse number of LCP0 in LCDCCR2 means enable time of LLP. This register
determines "High width" time as mentioned above. 1 pulse of this time in LCDCCR2
register is equal to 8 times of fsys regardless of LCP0 and LCP1. If "0" is written in
LCDCCR2 register, High level is output during the period that the valid data is output
from LD bus.
(In Mode1, high level is kept during one more LCP0 than valid data.)
LCD Clock Counter Register 0
7 6 5
LCD Clock Counter Register 1
7 6
× 14.5 or more). If "0" is written in LCDCCR1 register, fsys*14 to 16 of time is
SYS
LCD Clock Counter Register 2
7 6 5
LLPSU6 LLPSU5
R/W R/W R/W
0 0
TFT source driver, LLP_Enable signal: f
92CH21-363
4 3
5 4 3
TLDE4 TLDE3
R/W R/W
0 0
LLP_Set-up time: f
Set up time for TFT source driver LLP signal
(Offset of f
4 3
LLPSU4 LLPSU3
R/W R/W
0 0 0
High width time for LLP signal
TMP92CH21
2 1
PCPV2 PCPV1 PCPV0
R/W R/W
0 0
Pre LCP1 CLK: LCP1 pulse number
Dummy clock number until valid clock
of gate driver LCP1
2 1
TLDE2 TLDE1
R/W R/W
0 0
pulse × 8
SYS
14∼16 pulse)
SYS
2 1
LLPSU2 LLPSU1 LLPSU0
R/W R/W
0 0
× 8
SYS
2009-06-19
0
R/W
0
0
TLDE0
R/W
0
0
R/W
0