Toshiba TLCS-900/H1 Series Manual page 223
Original cmos 32-bit microcontroller
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3.10.3.15 FRAME Register
and is used for Isochronous transfer type.
FRAME_L
bit Symbol
(07E1H)
Read/Write
Reset State
bit Symbol
FRAME_H
Read/Write
(07E2H)
Reset State
T[10:7] (H register: Bit7 to bit4)
T[6:0] (L register: Bit6 to bit0)
CREATE (H register: Bit2)
0: DISABLE
1: ENABLE
FRAME STS[1:0]
(H register: Bit1 and bit0)
0: BEFORE
1: VALID
2: LOST
3.10.3.16 ADDRESS Register
enumeration.
ADDRESS
bit Symbol
(07E3H)
Read/Write
Reset State
ADDRESS [6:0] (Bit6 to bit0)
This register shows the frame number which is issued with SOF token from the host
Each HIGH and LOW register shows upper and lower bits.
7
6
−
T[6]
R
R
0
0
7
6
T[10]
T[9]
R
R
0
0
This register shows the device address which is specified by the host in bus
By reading this register, the present address can be confirmed.
7
6
A6
R
0
ID, and UDC judges whether it is an effective transaction or
not.
5
4
T[5]
T[4]
R
R
0
0
5
4
T[8]
T[7]
R
R
0
0
These bits are renewed when SOF-token is received.
They also show the frame-number.
These bits show whether the function that generates
SOF automatically from the UDC is enabled or not. This
is used in case of error in receiving SOF token.
This function is set by accessing COMMAND register.
On reset, this bit is initialized to "0".
These bits show the status whether a frame number
that is shown in the FRAME register is correct or not. At
the LOST status, a correct frame number is undefined.
If this register is "VALID", the number that is shown to
the FRAME register is correct.
If this register is "BEFORE", during SOF auto
generation, BEFORE condition shows it from USB host
controller inside that from SOF generation time to
reception of SOF token. Correct frame-number value is
the value that is selected from FRAME register value.
5
4
A5
A4
A3
R
R
0
0
The UDC compares this registers and address in all packet
This is initialized to "00H" by USB reset.
92CH21-221
3
2
T[3]
T[2]
T[1]
R
R
0
0
3
2
CREATE
FRAME_STS1 FRAME_STS0
R
0
3
2
1
A2
A1
R
R
R
0
0
0
TMP92CH21
1
0
T[0]
R
R
0
0
1
0
R
R
1
0
0
A0
R
0
2009-06-19
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