Toshiba TLCS-900/H1 Series Manual page 511

(3) Memory controller (2/3)
Symbol Name Address
BLOCK3
014CH
CS/WAIT
B3CSL
(Prohibit
control
RMW)
register low
BLOCK3
014DH
CS/WAIT
B3CSH (Prohibit
control
RMW)
register high
BLOCK EX
0158H
CS/WAIT
BEXCSL (Prohibit
control
RMW)
register low
BLOCK EX
0159H
CS/WAIT
BEXCSH (Prohibit
control
RMW)
register high
Page ROM
PMEMCR control 0166H
register
7 6 5
B3WW2 B3WW1
W
0 1
Write waits
001: 0 waits
101: 2 waits
011: (1 + N) waits
111: 4 waits
Others: Reserved
− −
B3E
0 0 0
CS select Always Always
0: Disable write "0". write "0".
1: Enable
BEXWW2 BEXWW1 BEXWW0
W
0 1
Write waits
001: 2 waits
101: 2 waits
011: (1 + N) waits
Others: Reserved
92CH21-509
4 3
B3WW0
0
010: 1 wait
110: 3 waits
B3REC B3OM1
W
0 0
Dummy 00: ROM/SRAM
cycle 01: Reserved
0:No 10: Reserved
insert 11: Reserved
1: Insert
0
010: 1 wait
110: 2 waits
BEXOM1
0
00: ROM/SRAM
01: Reserved
10: Reserved
11: Reserved
OPGE OPWR1
0 0
ROM Wait number on page
page
00: 1 CLK (n-1-1-1 mode)
access
01: 2 CLK (n-2-2-2 mode)
0: Disable
10: 3 CLK (n-3-3-3 mode)
1: Enable
11: Reserved
TMP92CH21
2 1 0
B3WR2 B3WR1 B3WR0
W
0 1 0
Read waits
001: 0 waits 010: 1 wait
101: 2 waits 110: 3 waits
011: (1 + N) waits
111: 4 waits
Others: Reserved
B3OM0 B3BUS1 B3BUS0
0 0/1 0/1
Data bus width
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
BEXWR2 BEXWR1 BEXWR0
W
0 1 0
Read waits
001: 2 waits 010: 1 wait
101: 2 waits 110: 2 waits
011: (1 + N) waits
Others: Reserved
BEXOM0 BEXBUS1 BEXBUS0
W
0 0/1 0/1
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
OPWR0 PR1 PR0
R/W
0 1 0
Byte number in page
00: 64 bytes
01: 32 bytes
10: 16 bytes
11: 8 bytes
2009-06-19