Toshiba TLCS-900/H1 Series Manual page 406

3.17.4.3 NAND-Flash Mode Control Register (ND0FMCR and ND1FMCR)
Bits Mnemonic
7 WE
6 ECC1
5 ECC0
4 CE
3 PCNT1
2 PCNT0
1 ALE
0 CLE
Figure 3.17.4 NAND-Flash Mode Control Register (ND0FMCR and ND1FMCR)
Field Name
Write enable Write enable (Default: 0)
This bit enables the data write operation. When writing the data to the NAND-Flash,
set this bit to "1".
When writing command or address, this bit need not be set to "1".
0: Disable write operation
1: Enable write operation
ECC control ECC control (Default: 00)
Control the ECC calculating circuits with <CE> (bit4) register.
11 (at<CE> = X): Reset ECC circuits
00 (at<CE> = 1): ECC circuits are disabled.
01 (at<CE> = 1): ECC circuits are enabled.
10 (at<CE> = 1): Read ECC data calculated by NDFC
10 (at<CE> = 0): Read ID data
Chip enable Chip enable (Default: 0)
Enable NAND-Flash access. Set "1" to this bit when accessing the NAND-Flash.
0: Disable (
1: Enable (
Power control Power control (Default: 00)
Always write "11"
Address latch Address latch enable (Default: 0)
enable
This bit specifies the value of the NDALE signal.
0: Low
1: High
Command latch Command latch enable (Default: 0)
enable
This bit specifies the value of the NDCLE signal.
0: Low
1: High
92CH21-404
7 6 5 4
WE ECC1 ECC0 CE
R/W R/W R/W R/W
0 0 0 0
Description
is High.)
NDCE
is Low.)
NDCE
TMP92CH21
3 5 1 0
PCNT1 PCNT0 ALE CLE
R/W R/W R/W R/W
0 0 0 0
2009-06-19
: Type
: Default