Toshiba TLCS-900/H1 Series Manual page 475

Page ROM Read Cycle
4.3.2
(1) 3-2-2-2 mode
No. Parameter
1 System clock period ( = T)
2 A0, A1 → D0 to D31 input
3 A2 to A23 → D0 to D31 input
falling → D0 to D31 input
4
RD
5 A0 to A23 Invalid → D0 to D31 hold
rising → D0 to D31 hold
6
RD
AC measuring condition
• Output: High = 0.7 VCC, Low = 0.3 VCC, C
• Input: High = 0.9 VCC, Low = 0.1 VCC
SDCLK
t
CYC
A0 to A23
CS 2
RD
D0 to D31
Symbol
t
CYC
t
AD2
t
AD3
t
RD3
t
HA
t
HR
= 50 pF
L
+0
t t
AD3 AD2
t t
RD3 HA
Data
input
92CH21-473
Variable
40 MHz 36 MHz 27 MHz Unit
Min Max
50 166.7
2.0T − 50
3.0T − 50
2.5T − 45
0
0
+1 +2
t
AD2
t
HA
Data Data
input
input
TMP92CH21
50 55.5 74
50 61 98
100 116.5 172
80 93.8 140
0 0 0
0 0 0
+3
t
HA
t
AD2
t
HR
t
HA
Data
input
2009-06-19
ns