Toshiba TLCS-900/H1 Series Manual page 410

3.17.4.8 NAND-Flash Reset Register (ND0FRSTR and ND1FRSTR)
Bits Mnemonic
−
7:1
0 RST
Note: After writing <RST> register, several waits are required (about 10 states) before accessing the NDFC.
Figure 3.17.9 NAND-Flash Reset Register (ND0FRSTR and ND1FRSTR)
3.17.4.9 NAND-Flash Control Register (NDCR)
NDCR Bit symbol CHSEL
(01C0H)
Read/Write
Reset State
Function
0: Channel 0
1: Channel 1
Field Name
−
Reserved
Reset Reset (Default: 0)
By setting this bit, reset the NDFC (except NDCR<CHSEL> register).
By reset, this bit is automatically cleared to "0".
0: Don't care
1: Reset
7 6 5
R/W
0
92CH21-408
7 6 5 4
Description
4 3
TMP92CH21
3 2 1 0
RST
R/W
0
2 1
2009-06-19
: Type
: Default
0