Toshiba TLCS-900/H1 Series Manual page 353

3.14.3.6 LCD Data Transmission Speed and Data Bus Occupation Rate
After setting start register, the LCDC outputs a bus release request to the CPU
and reads data from source memory. The LCDC then transmits LCD size data to
the external LCD driver through the special LCDC data bus (LD11 to LD0). At
this time, the control signals connected to the LCD driver output the specified
waveform which is synchronized with the data transmission. After data reading
from RAM for display is completed, the LCDC cancels the bus release request and
the CPU will restart.
During data read from source memory (during DMA operation), the CPU is
stopped by the internal BUSREQ signal. When using SR mode LCDC,
programmers must monitor CPU performance. The occupation rate of the data
bus depends on data size, transmission speed (CPU clock speed) and display RAM
type used.
Display RAM
External SRAM
Internal RAM
External SDRAM
Note: When using SDRAM for display RAM, overhead time (+ 8 clocks) is required for
every 1 row data reading.
t refers to the CPU stoppage time during transmission of 1 row data. t
STOP
is calculated by the equation below for each display mode.
t
STOP
SegNum
K
When SDRAM is used, more overhead time is required.
t
STOP
Data bus occupation rate equals the percentage of t
Data bus occupation rate = t
Note: For t
LP
Valid Data Reading Time
Bus Width
16 bits
32 bits
32 bits
16 bits
32 bits
= (SegNum × K/8) × t
LRD
: Number of segment
: bit number per pixel (bpp)
Monochrome
4 Grayscales
8/16 Grayscales
256 colors
4096 colors
= (SegNum × K/8) × t + ((1/f
LRD
STOP
time, refer to "refresh rate setting".
92CH21-351
(f Clock/Byte)
SYS
2/2
2/4
1/4
*1/2
*1/4
; Except SDRAM use
K = 1
K = 2
K = 4
K = 8
K = 12
) × 8)
; SDRAM use
SYS
STOP
/t
LP
TMP92CH21
Valid Data Reading Time
t (ns/Byte)
LRD
= 20 MHz
at f
SYS
50
25
12.5
*25
*12.5
STOP
time in t time.
LP
2009-06-19