Toshiba TLCS-900/H1 Series Manual page 317

3.12.2 Operation
The watchdog timer generates an INTWD interrupt when the detection time set in the
WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared to zero in software
before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway
occurs) due to causes such as noise, but does not execute the instruction used to clear the
binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
The CPU will detect malfunction (runaway) due to the INTWD interrupt, and in this case it
is possible to return the CPU to normal operation by means of an anti-malfunction
program.
The watchdog timer begins operating immediately on release of the watchdog timer
reset.
The watchdog timer is reset and halted in IDLE1 or STOP mode. The watchdog timer
counter continues counting during bus release (when
When the device is in IDLE2 mode, the operation of the WDT depends on the
WDMOD<I2WDT> setting. Ensure that WDMOD<I2WDT> is set before the device enters
IDLE2 mode.
The watchdog timer consists of a 22-stage binary counter which uses the clock φ (2/f
the input clock. The binary counter can output 2
WDT counter
WDT interrupt
WDT clear
(Software)
The runaway detection result can also be connected to the reset pin internally.
In this case, the reset time will be between 22 and 29 system clocks (35.2 to 46.4 μs at
f = 40 MHz) as shown in Figure 3.12.3. After a reset, the f
OSCH
f is generated by dividing the high-speed oscillator clock (f
FPH
clock gear function.
WDT counter
WDT interrupt
Internal reset
n Overflow
Figure 3.12.2 Normal Mode
Overflow
n
22 to 29 clocks (35.2 to 46.4 μs at f
Figure 3.12.3 Reset Mode
92CH21-315
goes low).
BUSAK
/f , 2 /f , 2 /f and 2
15 17 19
IO IO IO
Write clear code
clock is f
IO
) by sixteen through the
OSCH
= 40 MHz)
OSCH
TMP92CH21
) as
IO
/f .
21
IO
0
/4, where
FPH
2009-06-19