Toshiba TLCS-900/H1 Series Manual page 387

SDCLK
SDCKE
SDUUDQM
SDULDQM
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE
A10
RA
A15 to A0
RA
D31 to D0
Bank active
SDCLK
SDCKE
SDUUDQM
SDULDQM
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE
A10
A15 to A0
D31 to D0
(Structure of Data Bus: 32 bits × 1, operand Size: 4 bytes, address: 4 n + 0)
85 states (320-byte read)
CA (n + 4) CA (n + 8)
CA (n + 12)
CA (n)
D (n + 4)
D (n)
Read
Figure 3.16.2 Timing of Burst Read Cycle
3 states
RA
RA
OUT
Bank active
Figure 3.16.3 Timing of CPU Write Cycle
92CH21-385
(n + 312) (n + 316)
D (n + 8) D (n + 12)
CA
CA
Write with Internal
precharge precharge
TMP92CH21
D (n + 312) D (n + 316)
All banks
precharge
2009-06-19