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Toshiba TLCS-900/H1 Series Manual page 304

Original cmos 32-bit microcontroller
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3.10.11 Notice and Restrictions
1.
Limitation of writing to COMMAND register in special timing
When "STALL" command is issued, ENDPOINT status might shift to "INVALID". To
avoid this problem, follow the routine below.
a.
BULK (IN/OUT)
When issuing a STALL command to endpoint in BULK transfer, be sure to issue
STALL command after stopping RD/WR access to endpoint; that is UDC returns
NAK in response to token from host. INT_EPxNAK should be used to detect NAK
transmit.
b.
CONTROL OUT with data stage (software response)
If STALL needs to be set for endpoint 0 judging from request after receiving
INT_SETUP interrupt, access SetupReceived register. After that, issue STALL
command after detecting INT_ENDPOINT0 interrupt.
c.
CONTROL OUT without data stage (software response)
If STALL needs to be set for endpoint 0 judging from request after receiving
INT_SETUP interrupt, issue STALL command before access to eop register.
d.
CONTROL IN(software response)
If STALL needs to be set for endpoint 0 judging from request after receiving
INT_SETUP interrupt, issue STALL command before setting the first transmit
data to host.
2.
Limitation of EPx_STATUS<STATUS2:0> when executing USB_RESET command
EPx_STATUS<STATUS2:0> may indicate different condition, if aUSB_RESET
command is executed to the endpoint processing the token. To avoid this phenomenon,
do not RESET the endpoint while transferring. (It is available when processing a
request that needs USB_RESET to that endpoint.)
92CH21-302
TMP92CH21
2009-06-19

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