Toshiba TLCS-900/H1 Series Manual page 116

Original cmos 32-bit microcontroller

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(5) Recovery (Data hold) cycle control

Some memory is defined by AC specification about data hold time by

read cycle. Therefore, a data conflict problem may occur. To avoid this problem,

1-dummy cycle can be inserted after CSm-block access cycle by setting "1" to

BmCSH<BmREC> register.

This 1-dummy cycle is inserted when the next cycle is for another CS-block.

When no dummy cycle is inserted (0 waits)

When inserting a dummy cycle (0 waits)

<BnREC> (BnCSH register)

No dummy cycle is inserted (Default).

Dummy cycle is inserted.

Tmp92ch21fg Jtmp92ch21