Toshiba TLCS-900/H1 Series Manual page 246

Below is control flow in UDC as seen from application.
Start up
Setting each EP mode
in Set_Config (Interface)
Enumeration
Control RD transfer
Get_Vendor_Request
process
EP0 bit = 1
EP0 bit = 0
Check
DATASET
register
Total ≥ payload
WR number of payload
to EP0_FIFO register
Total = Total − payload
Receive
except
INT_STATUS
Abnormal
finish
Normal
finish
Receive
INT_STATUS
Figure 3.10.2 Control Flow in UDC as seen from Application
Note : This chart does not cover special cases such as overlap receive SETUP packet.
Please refer to chapter of 3.10.6 (2) (c)Control transfer type.
IDLE
Identify request RD
Access to SetupReceived register
Transmit
Total_Length calculation
Total < payload
WR number of rest data
to EP0_FIFO
Total = 0
Status finish
process in UDC
92CH21-244
Standard request
Printerclass request
Control WR transfer
Set_Vendor_Request
EP0 bit = 0
EP0 bit = 1
Check
DATASET
register
Total > payload
RD number of payload RD number of rest data
from EP0_FIFO register from EP0_FIFO
Total = Total − payload
Total = 0
WR "0" only EP0 bit0 of
EOP register
TMP92CH21
process
Receive
Total_Length calculation
Total ≤ payload Total = 0
Not
processed
Total = 0
2009-06-19