Toshiba TLCS-900/H1 Series Manual page 336

LCDSIZE Bit symbol
(0284H)
Read/Write
Reset State
Function Common setting
0000: Reserved
0001: 64
0010: 120
0011: 128
0100: 160
Note 1: Maximum size in color mode (STN,TFT) is 320 × 320.
When internal SRAM is set as display RAM, the maximum size is as below.
1 bpp (Monochrome):
2 bpp (4 grayscales):
4 bpp (16 grayscales): 256 × 128
8 bpp (256 colors):
12 bpp (4096 colors):
Note 2: This LSI does not support 240-segment size, but if a cascade type segment driver is selected, it can used
by setting for 256-segment size. In this case, a 256-segment display area must be prepared.
LCDCTL0 Bit symbol
(0285H)
Read/Write
Reset State
Function
LCDCTL1 Bit symbol
(0286H)
Read/Write
Reset State
Function LCP0 phase
0: Rise
1: Fall
LCDSCC Bit symbol
(0287H)
Read/Write
Reset State
Function
LCD Size Setting Register
7 6
COM3 COM2 COM1
R/W R/W R/W
0 0
0101: 200
0110: 240
0111: 320
1000: 480
Others: Reserved
640 × 200
320 × 200
128 × 128
128 × 64
LCD Control-0 Register
7 6
ALL0 FRMON
R/W R/W
0
Column Frame
divide
data setting
setting
0: Normal
0: Disable
1: All display
1: Enable
data "0"
LCD Control-1 Register
7 6
LCP0P LCP1P LBCDP
R/W R/W R/W
1 0
LCP1 phase LBCD phase
0: Rise 0: Low
1: Fall enable
1: High
enable
LCDC Source Clock Counter Register
7 6
SCC7 SCC6 SCC5
0 0
5 4 3
COM0 SEG3
R/W R/W
0 0 0
Segment setting
0000: Reserved 0101: 320
0001: 64
0010: 128
0011: 160
0100: 256
5 4 3
−
FP9
R/W R/W
0 0 0
Always f setting
FP
write "0".
bit9
5 4 3
1
5 4 3
SCC4 SCC3
R/W
0 0 0
LCDC source clock counter bit7 to bit0
92CH21-334
TMP92CH21
2 1
SEG2 SEG1
R/W R/W
0 0
0110: 480
0111: 640
1000: 768
1001: 960 Others: Reserved
2 1
MMULCD FP8
R/W R/W
0 0
f setting LCDC start
Built-in RAM
FP
bit8 0: Stop
LCD driver
1: Start
setting
0: Sequential
access
1: Random
access
2 1
LBCDW1 LBCDW0
R/W
0
LBCD width control
00 : LCP1_1CLK
01 : LCP1_2CLK
10 : LCP1_3CLK
11 : Reserved
2 1
SCC2 SCC1
0 0
2009-06-19
0
SEG0
R/W
0
0
START
R/W
0
0
R/W
0
0
SCC0
0