Toshiba TLCS-900/H1 Series Manual page 261

SETUP DATA0 ACK
INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR
bmRequestType register
bRequest register
wValue register
wIndex register
wLength register
Figure 3.10.7 The Control Flow in UDC (Control Write Transfer Type)
correspond with the data number specified by the device request. The CPU can
therefore process using INT_STATUSNAK interrupt. However, when class and
vendor request is used, wLength value corresponds to data transfer number in
data phase. With this setting, using this interrupt is not need. Data stage data
can be confirmed by accessing DATASIZE register.
Stage change condition of control writes transfer type
1. Receive SETUP token from host.
• Start setup stage in the UDC.
•
Receive data in request normally and judge. And assert INT_SETUP
interrupt externally.
•
Change data stage in the UDC.
2. Receive OUT token from host.
• CPU receives a request from the request register every INT_SETUP
interrupt.
• Judge request and access Setup Received register for inform the UDC
that INT_SETUP interrupt has been recognized.
• Receive dataphase data normally, and set EP0 bit of DATASET
register.
•
The CPU receives data in FIFO by setting DATASET.
• The CPU processes receiving data by device request.
• When the CPU finishes transaction, it writes "0" to EP0 bit of EOP
register.
•
Change status stage in the UDC.
3. Receive IN token from host.
•
Return data packet of 0 data to IN token and change state to IDLE in
the UDC.
• Assert INT_STATUS interrupt externally when ACK for 0 data
packet is received.
These changing conditions are shown in Figure 3.10.7.
OUT DATA1 ACK OUT DATA0
Setup Received register
In control read transfer type, transaction number of data stage does not always
92CH21-259
NAK OUT DATA0 ACK
EP0_FIFO (Rest data)
EP0_FIFO (RD of payload)
TMP92CH21
IN NAK IN DATA1
EOP register
2009-06-19
ACK