Toshiba TLCS-900/H1 Series Manual page 335

3.14.2 SFRs
LCDMODE0 Bit symbol RAMTYPE1 RAMTYPE0
(0280H)
Read/Write
Reset State
Function Display RAM
00: Internal SRAM
01: External SRAM
10: SDRAM
11: Reserved
Note: Only "burst 1clk access" SDRAM access is supported
LCDMODE1 Bit symbol
(0281H)
Read/Write
Reset State
Function
When using TFT mode, LD bus width is fixed below setting. Set "10" to <LDO1:0> for
256-color. For 4096-color, setting <LDO1:0> is not needed, but bus-width becomes 12-bit
automatically.
Note: When setting <LDINV> = 1, auto LD bus inversion function does not work.
<LDINV> = 0 must be set if you want to use auto LD bus inversion function.
LCDFFP Bit symbol
(0282H)
Read/Write
Reset State
Function
LCDDVM Bit symbol
(0283H)
Read/Write
Reset State
Function
LCDMODE0 Register
7 6 5
SCPW1
R/W R/W R/W
0 0 1
LD bus transmission
speed
00: Reserved
01: 2 × f
10: 4 × f
11: 8 × f
LCDMODE1 Register
7 6 5
LLPMODE
R/W
0
LLP mode
0: Mode 1
1: Mode 2
LCD f
7 6 5
FP7 FP6 FP5
0 0 0
Divide FRM Register
7 6 5
FMN7 FMN6 FMN5
0 0 0
92CH21-333
4 3
SCPW0 MODE3
R/W R/W
0 0
Mode setting
0000: Built-in RAM type
0001: SR 1 bpp
SYS 0010: SR 2 bpp (4 grayscales)
SYS 0011: SR 3 bpp (8 grayscales)
SYS
0100: SR 4 bpp
4 3
LDINV AUTOINV
R/W R/W
0 0
LD bus Auto LD bus
inversion inversion
(Note 1) 0: Disable
0: Normal 1: Enable
1: Inversion (Valid in
TFT mode)
Register
FP
4 3
FP4 FP3
R/W
0 0
Setting bit7 to bit0 for f
FP
4 3
FMN4 FMN3
R/W
0 0
Setting DVM bit7 to bit0
TMP92CH21
2 1
MODE2 MODE1 MODE0
R/W R/W
0 0
0101: STN 8 bpp (256 colors)
0110: STN 12 bpp (4 K colors)
(monochrome)
0111: Reserved
1000: TFT 8 bpp (256 colors)
1001: TFT 12 bpp (4 K colors)
(16 grayscales)
Others: Reserved
2 1
INTMODE LDO1
R/W R/W
0 0
Interrupt LD bus width control
select 00: 4-bit width A type
0: LP 01: 4-bit width B type
1: BCD 10: 8-bit width A type
11: 8-bit width B type
2 1
FP2 FP1
0 0
2 1
FMN2 FMN1
0 0
2009-06-19
0
R/W
0
0
LDO0
R/W
0
0
FP0
0
0
FMN0
0