Toshiba TLCS-900/H1 Series Manual page 133

3.7.3 SFR
TA01RUN Bit symbol TA0RDE
(1100H)
Read/Write
Reset State
Function Double
buffer
0: Disable
1: Enable
TA0REG double buffer control
0
1
Note: The values of bits 4 to 6 of TA01RUN are undefined when read.
TA23RUN Bit symbol TA2RDE
(1108H)
Read/Write
Reset State
Function Double
buffer
0: Disable
1: Enable
TA2REG double buffer control
0
1
Note: The values of bits 4 to 6 of TA23RUN are undefined when read.
Figure 3.7.4 TMRA01 Run Register and TMRA23 Run Register
TMRA01 Run Register
7 6 5
R/W
0
Disable
Enable
TMRA23 Run Register
7 6 5
R/W
0
Disable
Enable
92CH21-131
4 3 2
I2TA01 TA01PRUN
0 0
IDLE2 TMRA01
0: Stop prescaler
1: Operate
0: Stop and clear
1: Run (Count up)
4 3 2
I2TA23 TA23PRUN
0 0
IDLE2 TMRA23
0: Stop prescaler
1: Operate
0: Stop and clear
1: Run (Count up)
TMP92CH21
1 0
TA1RUN TA0RUN
R/W
0 0
UP counter UP counter
(UC0)
(UC1)
Timer run/stop control
0 Stop and clear
1 Run (Count up)
1 0
TA3RUN TA2RUN
R/W
0 0
UP counter UP counter
(UC2)
(UC3)
Timer run/stop control
0 Stop and clear
1 Run (Count up)
2009-06-19