Toshiba TLCS-900/H1 Series Manual page 14

3. Operation
This section describes the basic components, functions and operation of the TMP92CH21.
3.1 CPU
The TMP92CH21 contains an advanced high-speed 32-bit CPU (TLCS-900/H1 CPU)
3.1.1 CPU Outline
The TLCS-900/H1 CPU is a high-speed, high-performance CPU based on the
TLCS-900/L1 CPU. The TLCS-900/H1 CPU has an expanded 32-bit internal data bus to
process instructions more quickly.
The following is an outline of the CPU:
Table 3.1.1 TMP92CH21 Outline
Parameter
Width of CPU address bus
Width of CPU data bus
Internal operating frequency
Minimum bus cycle
Internal RAM
Internal boot ROM
Internal I/O
External SRAM, Masked ROM
External SDRAM
External NAND flash
Minimum instruction
execution cycle
Conditional jump
Instruction queue buffer
Instruction set
CPU mode
Micro DMA
92CH21-12
TMP92CH21
24 bits
32 bits
Max 20 MHz
1-clock access (50 ns at f
SYS
32-bit 1-clock access
32-bit 2-clock access
8- or 16-bit 2-clock access or
8- or 16-bit 5 to 6-clock access
8- or 16- or 32-bit 2-clock access
(waits can be inserted)
16- or 32-bit min. 1-clock access
8-bit min. 4-clock access
(waits can be inserted)
1-clock (50 ns at f =20MHz)
SYS
2-clock (100 ns at f =20MHz)
SYS
12 bytes
Compatible with TLCS-900/L1
(LDX instruction is deleted)
Maximum mode only
8 channels
TMP92CH21
= 20MHz)
2009-06-19