Toshiba TLCS-900/H1 Series Manual page 36

3.3.6 Stand-by Controller
(1) HALT modes and port drive register
When the HALT instruction is executed, the operating mode switches to IDLE2,
IDLE1 or STOP mode, depending on the contents of the SYSCR2<HALTM1:0> register
and each pin-status is set according to the PxDR register, as shown below:
PxDR Bit symbol
(xxxxH)
Read/Write
Reset state
Function
(Purpose and use)
•
This register is used to set each pin status at stand-by mode.
•
All ports have this registers of the format shown above. ("x" indicates the port name.)
•
For each register, refer to 3.5 function of ports.
•
Before "Halt" instruction is executed, set each register according to the expected pin status. They will be effective
after the CPU has executed the "Halt" instruction.
•
This is the case regardless of stand-by mode (IDLE2, IDLE1 or STOP).
•
The Output/Input buffer control table is shown below.
Note 1: OE denotes an output enable signal before stand-by mode.
Basically, PxCR is used as OE.
Note 2: "n" in PxnD denotes the bit number of PORTx
The subsequent actions performed in each mode are as follows:
1.
2.
3.
7 6
Px7D Px6D Px5D
1 1
Output/input buffer drive register for stand-by mode
OE PxnD Output Buffer
0 0 OFF
0 1 OFF
1 0 OFF
1 1 ON
IDLE2: only the CPU halts.
The internal I/O is available to select operation during IDLE2 mode by setting
the following register.
Table 3.3.3 shows the register setting operation during IDLE2 mode.
Table 3.3.3 SFR Setting Operation during IDLE2 Mode
Internal I/O
TMRA01
TMRA23
TMRB0
SIO0
SIO1
AD converter
WDT
IDLE1: Only the oscillator, RTC (real-time clock) and MLD continue to operate.
STOP: All internal circuits stop operating.
5 4 3
Px4D Px3D
R/W
1 1 1
Input Buffer
OFF
ON
OFF
OFF
SFR
TA01RUN<I2TA01>
TA23RUN<I2TA23>
TB0RUN<I2TB0>
SC0MOD1<I2S0>
SC1MOD1<I2S1>
ADMOD1<I2AD>
WDMOD<I2WDT>
92CH21-34
TMP92CH21
2 1 0
Px2D
Px1D Px0D
1 1
2009-06-19
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