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Toshiba TLCS-900/H1 Series Manual page 401

Original cmos 32-bit microcontroller
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3)
Read
The read sequence is as follows.
(1) ND0FMCR:
(2) Read 512 bytes
ND0FMCR:
ND0FDTR:
ND0FMCR:
ND0FDTR:
ND0FMCR:
Wait several states (e.g., "NOP" × 10)
ND0FSR:
ND0FMCR:
ND0FDTR:
ND0FMCR:
ND0FDTR:
(3) Read ECC data
ND0FMCR:
NDECCRD:
First data:
Second data:
Third data:
Fourth data:
Fifth data:
Sixth data:
(4) Software routine:
Compare ECC data and redundant data, run the error routine if error is
generated.
(5) Read other pages
ND0FMCR:
ND0FSR:
Set 0x7C for ECC data reset.
Set 0x1D for NDCLE signal enable and command mode.
Set 0x00 for the read command.
Set 0x1E for NDALE signal enable and address mode.
Set A [7:0], A [16:9], and A [24:17]. If it is required, set A
[25].
Set 0x1C for NDALE signal disable.
Check BUSY flag. If it is 0, go to the next.
If it is 1, wait until it becomes 0.
Set 0x3C for the data mode with ECC calculation.
Read 512-byte data.
Set 0x1C for the data mode without ECC calculation.
Read 16-byte redundant data.
Set 0x5C for the ECC data read mode.
Read 6-byte ECC data.
LPR [7:0]
LPR [15:8]
CPR [5:0], 2'b11
LPR [23:16]
LPR [31:24]
CPR [11:6], 2'b11
Set 0x1C.
Check BUSY flag. If it is 0, go to the next.
If it is 1, wait until it becomes 0.
92CH21-399
TMP92CH21
2009-06-19

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