Toshiba TLCS-900/H1 Series Manual page 38
Original cmos 32-bit microcontroller
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Table 3.3.5 Source of Halt State Clearance and Halt Clearance Operation
Status of Received Interrupt
HALT Mode
INTWD
INT0 to INT4 (Note 1)
INTALM0 to INTALM4
INTTA0 to INTTA3,
INTTB0 to INTTB1
INTRX0 to INTRX1,
TX0 to TX1
INTTBO0, INTI2S
INTAD, INT5
INTKEY
INTRTC
INTUSB
INTLCD
RESET
♦: After clearing the HALT mode, CPU starts interrupt processing.
○
: After clearing the HALT mode, CPU resumes executing starting from the instruction following the HALT
instruction.
×: Cannot be used to release the HALT mode.
−: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority
level. This combination is not available.
*1: Release of the HALT mode is executed after warm-up time has elapsed.
*2: 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode, allowing for the
construction of low power dissipation systems. However, the method of use is limited as below.
Shift to IDLE1 mode :
Execute Halt instruction when the flag of INT_SUS or INT_CLKSTOP is "1" ( SUSPEND state )
Release from IDLE1 mode :
Release Halt state by INT_RESUME or INT_CLKON request (release SUSPEND request)
Release Halt state by INT_URST_STR or INT_URST_END request (RESET request)
Example: Releasing IDLE1 mode
An INT0 interrupt clears the halt state when the device is in IDLE1 mode.
Address
8200H
LD
8203H
LD
8206H
LD
8209H
EI
820BH
LD
820EH
HALT
INT0
820FH
LD
Interrupt Enabled
Interrupt level) ≥ (Interrupt mask)
(
IDLE2
IDLE1
♦
×
♦
♦
♦
♦
♦
×
♦
×
♦
×
♦
×
♦
♦
♦
♦
♦
♦* 2
♦
×
(PCFC), 01H
(IIMC), 00H
(INTE0AD), 06H
5
(SYSCR2), 28H
XX, XX
92CH21-36
Interrupt level) < (Interrupt mask)
(
STOP
IDLE2
×
−
○
♦* 1
○
×
×
×
×
×
×
×
×
×
○
♦* 1
○
♦* 1
○
×
×
×
Initialize LSI
;
Sets PC0 to INT0.
;
Selects INT0 interrupt rising edge.
;
Sets INT0 interrupt level to 6.
;
Sets interrupt level to 5 for CPU.
;
Sets HALT mode to IDLE1 mode.
;
Halts CPU.
TMP92CH21
Interrupt Disabled
IDLE1
STOP
−
−
○
○
* 1
○
×
×
×
×
×
×
×
×
×
○
○
* 1
○
○
* 1
○
×
* 2
×
×
INT0 interrupt routine
RETI
2009-06-19
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