Toshiba TLCS-900/H1 Series Manual page 225
Original cmos 32-bit microcontroller
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3.10.3.18 Port Status Register
Port Status
bit Symbol
(07E0H)
Read/Write
Reset State
Note: The TMP92CH21 does not use this register since it does not support printer-class.
3.10.3.19 Standard Request Mode Register
Note: With Automatic Set_Interface request answer, requests to interface 4 to 6 may not become request errors. If
bit Symbol
Standard Request Mode
(07D8H)
Read/Write
Reset State
S_Intetface
G_Interface
S_Config
G_Config
G_Descript
S_Feature
C_Feature
G_Status
This register is used when a printer class request is received.
In the case of a GET_PORT_STATUS request, the UDC operates automatically
using this data.
7
6
Reserved7
Reserved6
W
W
0
0
The data should be written before receiving request. Write "0" to the <Reserved> bit
of this register. This register is initialized to "18H" on reset.
This register sets the answer for Standard Request, either answering automatically
in hardware, or by control through software. Each bit represents a kind of request.
When the relevant bit in this register is set to "0", the answer is executed
automatically by hardware. When the relevant bit in this register is set to "1", the
answer is controlled by software. If a request is received during hardware control, the
interrupt signal (INT_SETUP, INT_ENDPOINT0, INT_STATUS, INT_STATUSNAK)
is set to disable. If a request is received during software control, the interrupt signal is
asserted, and it is controlled by software.
this is a problem, in Set_Interface request answer, set Standard Request Mode <S_INTERFACE> to "1" and
use software.
7
6
S_Interface
G_Interface
R/W
R/W
0
0
(Bit 7) : SET_INTERFACE
(Bit 6) : GET_INTERFACE
(Bit 5) : SET_CONFIGRATION
(Bit 4) : GET_CONFIGRATION
(Bit 3) : GET_DESCRIPTOR
(Bit 2) : SET_FEATURE
(Bit 1) : CLEAR_FEATURE
(Bit 0) : GET_STATUS
5
4
PaperError
Select
NotError
W
W
0
1
5
4
S_Config
G_Config
R/W
R/W
0
0
92CH21-223
TMP92CH21
3
2
1
Reserved2
Reserved1
W
W
W
1
0
0
3
2
G_Descript
S_Feature
C_Feature
R/W
R/W
R/W
0
0
0
Reserved0
W
0
1
0
G_Status
R/W
0
0
2009-06-19
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