Toshiba TLCS-900/H1 Series Manual page 404

3.17.4.1 NAND-Flash Data Transfer Register (ND0FDTR and ND1FDTR)
Bit (s) Mnemonic
7:0 DATA
Note 1: This register has a 512-address window from 1D00H to 1EFFH since a NAND-Flash page size is either 256
or 512 bytes.
When the CPU reads from or writes to the NAND-Flash , and if the block transfer instruction ("LDIR"
instruction) is used, the following restriction applies to the 900/H1 CPU.
[Restriction for using the block transfer instruction]
1) The source address for "LDIR" instruction should be set to (1F00H – read (or write) byte number)
Example 1) In case of 512-byte read
Example 2) In case of 16-byte read
Note 2: Both ND0FDTR and ND1FDTR are assigned to the same address. The NDCR<CHSEL> register
determines which channel is accessed.
Figure 3.17.2 NAND-Flash Data Transfer Register (ND0FDTR and ND1FDTR)
Field Name
DATA NAND-Flash data.
Read: Read the data that was read from the NAND-Flash.
Write: Write data to the NAND-Flash.
ld bc, 512
ld xix, 2000H
ld xiy, 1D00H
(xix + ), (xiy + )
ldir
ld bc, 16
ld xix, 2000H
ld xiy, 1EF0H
(xix + ), (xiy + )
ldir
92CH21-402
7
DATA
R/W
−
Description
; 512 bytes
; dst = 2000H
; src = (1F00H − 512) = 1D00H
; Block transfer instruction
; 16 bytes
; dst = 2000H
; src = (1F00H − 16) = 1EF0H
; Block transfer instruction
TMP92CH21
0
: Type
: Default
2009-06-19