Toshiba TLCS-900/H1 Series Manual page 44

3.4 Interrupts
Interrupts are controlled by the CPU Interrupt mask register <IFF2:0> (bits12 to 14 of the
status register) and by the built-in interrupt controller.
The TMP92CH21 has a total of 50 interrupts divided into the following five types:
Interrupts generated by CPU: 9 sources
Software interrupts: 8 sources
Illegal instruction interrupt: 1 source
Internal interrupts: 34 sources
Internal I/O interrupts: 26 sources
Micro DMA transfer end interrupts: 8 sources
External interrupts: 7 sources
Interrupts on external pins (INT0 to INT5, INTKEY)
A fixed individual interrupt vector number is assigned to each interrupt source.
Any one of six levels of priority can also be assigned to each maskable interrupt.
Non-maskable interrupts have a fixed priority level of 7, the highest level.
When an interrupt is generated, the interrupt controller sends the priority of that interrupt
to the CPU. When more than one interrupt is generated simultaneously, the interrupt
controller sends the priority value of the interrupt with the highest priority to the CPU. (The
highest priority level is 7, the level used for non-maskable interrupts.)
The CPU compares the interrupt priority level which it receives with the value held in the
CPU interrupt mask register <IFF2:0>. If the priority level of the interrupt is greater than or
equal to the value in the interrupt mask register, the CPU accepts the interrupt.
However, software interrupts and illegal instruction interrupts generated by the CPU are
processed irrespective of the value in <IFF2:0>.
The value in the interrupt mask register <IFF2:0> can be changed using the EI instruction
(EI num sets <IFF2:0> to num). For example, the command EI 3 enables the acceptance of all
non-maskable interrupts and of maskable interrupts whose priority level, as set in the
interrupt controller, is 3 or higher. The commands EI and EI 0 enable the acceptance of all
non-maskable interrupts and of maskable interrupts with a priority level of 1 or above (hence
both are equivalent to the command EI 1).
The DI instruction (sets <IFF2:0> to 7) is exactly equivalent to the EI 7 instruction. The DI
instruction is used to disable all maskable interrupts (since the priority level for maskable
interrupts ranges from 1 to 6). The EI instruction takes effect as soon as it is executed.
In addition to the general purpose interrupt processing mode described above, there is also a
micro DMA processing mode.
In micro DMA mode the CPU automatically transfers data in one-byte, two-byte or four-byte
blocks; this mode allows high-speed data transfer to and from internal and external memory
and internal I/O ports.
In addition, the TMP92CH21 also has a software start function in which micro DMA
processing is requested in software rather than by an interrupt.
Figure 3.4.1 is a flowchart showing overall interrupt processing.
92CH21-42
TMP92CH21
2009-06-19