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(a) Interrupt enable flag (IE)
(b) Zero flag (Z)
(c) Register bank select flags (RBS0 and RBS1)
(d) Auxiliary carry flag (AC)
(e) In-service priority flag (ISP)
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(f) Carry flag (CY)
This flag controls interrupt request acknowledge operations of CPU.
When IE = 0, the IE is set to interrupt disabled (DI) status. All interrupt requests except non-maskable interrupt
are disabled.
When IE = 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledgement is controlled
with an inservice priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority
specification flag.
This flag is reset to (0) upon DI instruction execution or interrupt request acknowledgment and is set to (1)
upon EI instruction execution.
When the operation result is zero, this flag is set to (1). It is reset to (0) in all other cases.
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction
execution is stored.
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to (1). It is reset to (0) in
all other cases.
This flag manages the priority of acknowledgeable maskable vectored interrupts.
When ISP = 0, acknowledgment of the vectored interrupt request specified to low-order priority with the
priority specify flag registers (PR0L and PR0H) (refer to 18.3 (3) Priority specify flag registers (PR0L,
PR0H)) is disabled. Whether an actual interrupt request is acknowledged or not is controlled with the interrupt
enable flag (IE).
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction
execution.
CHAPTER 5 CPU ARCHITECTURE
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