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Caution
TCL13
0
0
0
0
1
1
1
1
1
1
1
1
Other than above
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Remarks 1. f
CHAPTER 9 8-BIT TIMER/EVENT COUNTER
Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the CR10
value, interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter output
control circuit 1 is inverted. Thus, when using 8-bit timer/event counter as 16-bit interval timer,
set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment.
When reading 16-bit timer (TMS) count value, use the 16-bit memory manipulation instruction.
Table 9-9. Interval Times when 2-Channel 8-Bit Timer/Event Counters
(TM1 and TM2) are Used as 16-Bit Timer/Event Counter
TCL12
TCL11
TCL10
0
0
0
TI1 input cycle
0
0
1
TI1 input cycle
1
1
0
2
1
1
1
2
0
0
0
2
0
0
1
2
0
1
0
2
0
1
1
2
1
0
0
2
1
0
1
2
1
1
0
2
1
1
1
2
Setting prohibited
: Main system clock oscillation frequency
X
2. TCL10 to TCL13: Bits 0 to 3 of the timer clock select register 1 (TCL1)
3. Values in parentheses apply to operation with f
Minimum Interval Time
Maximum Interval Time
2
8
8
2
× 1/f
2
18
(400 ns)
2
X
× 1/f
3
(800 ns)
2
19
X
× 1/f
(1.6 µ s)
4
20
2
X
× 1/f
(3.2 µ s)
5
2
21
X
(6.4 µ s)
× 1/f
6
2
22
X
× 1/f
(12.8 µ s)
7
23
2
X
× 1/f
(25.6 µ s)
8
2
24
X
(51.2 µ s)
× 1/f
9
2
25
X
× 1/f
(102.4 µ s)
10
26
2
X
× 1/f
(409.6 µ s)
12
2
28
X
= 10.0 MHz.
X
× TI1 input cycle
TI1 input edge cycle
× TI1 input cycle
TI1 input edge cycle
× 1/f
× 1/f
2
(26.2 ms)
2
X
× 1/f
× 1/f
(52.4 ms)
2
3
X
× 1/f
× 1/f
4
(104.9 ms)
2
X
× 1/f
× 1/f
(209.7 ms)
2
5
X
× 1/f
× 1/f
(419.4 ms)
2
6
X
× 1/f
× 1/f
7
(838.9 ms)
2
X
× 1/f
× 1/f
(1.7 s)
2
8
X
× 1/f
× 1/f
(3.4 s)
2
9
X
× 1/f
× 1/f
10
(6.7 s)
2
X
× 1/f
× 1/f
(26.8 s)
2
12
X
Resolution
(400 ns)
X
(800 ns)
X
(1.6 µ s)
X
(3.2 µ s)
X
(6.4 µ s)
X
(12.8 µ s)
X
(25.6 µ s)
X
(51.2 µ s)
X
(102.4 µ s)
X
(409.6 µ s)
X
217
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