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(6) Address match detection method
2
In the I
C mode, the master can select a specific slave device by sending slave address data.
Address match detection is performed automatically by the slave device hardware. CSIIF0 is set only when a
slave device address has a slave register (SVA), the wake-up function specification bit (WUP) is 1, and the slave
address sent from the master device matches with the address set in SVA.
When bit 5 (SIC) of the interrupt timing specification register (SINT) is set to 1, the wake-up function does not
operate if WUP is set to 1. (In the detection of stop condition, an interrupt request signal is generated.) When
wake-up function is used, clear SIC to 0.
Caution Slave selection/non-selection is detected by matching of the slave address received after bus
release.
For this match detection, match interrupt request (INTCSI0) of the address to be generated with
WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave address
when WUP = 1.
(7) Error detection
2
In the I
C bus mode, transmission error detection can be performed by the following methods because the serial
bus SDA0 (SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0) of the
transmitting device.
(a) Comparison of SIO0 data before and after transmission
In this case, a transmission error is judged to have occurred if the two data values are different.
(b) Using the slave address register (SVA)
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Transmit data is set in SIO0 and SVA before transmission is performed. After transmission, the COI bit (match
signal from the address comparator) of serial operating mode register 0 (CSIM0) is tested: "1" indicates
normal transmission, and "0" indicates a transmission error.
(8) Communication operation
2
In the I
C bus mode, the master selects the slave device to be communicated with from among multiple devices
by outputting address data onto the serial bus.
After the slave address data, the master sends the R/W bit which indicates the data transfer direction, and starts
serial communication with the selected slave device.
Data communication timing charts are shown in Figures 16-45 and 16-46.
In the transmitting device, serial I/O shift register 0 (SIO0) shifts transmission data to the SO latch in
synchronization with the falling edge of the serial clock (SCL), the SO0 latch outputs the data on an MSB-first
basis from the SDA0 or SDA1 pin to the receiving device.
In the receiving device, the data input from the SDA0 or SDA1 pin is taken into SIO0 in synchronization with the
rising edge of SCL.
392
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
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