Table of Contents
Advertisement
Signal Name
Output
Definition
Device
Serial clock
Master
Synchronous clock to
(SCK0)
output address/command/
data, ACK signal, synchro-
nization BUSY signal, etc.
Address/command/data
are transferred with the
first eight synchronous
clocks.
Address
Master
8-bit data to be transferred
(A7 to A0)
in synchronization with
SCK0 after output of REL
and CMD signals
Address
Master
8-bit data to be transferred
(C7 to C0)
in synchronization with
SCK0 after output of only
CMD signal without REL
signal output
Address
Master/
8-bit data to be transferred
(D7 to D0)
slave
in synchronization with
SCK0 without output of
REL and CMD signals
Notes
1. When WUP = 0, CSIIF0 is set at the rising edge of the 9th clock of SCK0.
When WUP = 1, an address is received. Only when the address matches the slave address register (SVA), CSIIF0 is set (when the address does not match,
RELD is cleared).
2. In BUSY state, transfer starts after the READY state is set.
Table 16-5. Various Signals in SBI Mode (2/2)
Timing Chart
1
2
7
8
SCK0
SB0 (SB1)
1
2
7
SCK0
SB0 (SB1)
REL
CMD
1
2
7
SCK0
SB0 (SB1)
CMD
1
2
7
SCK0
SB0 (SB1)
CMD
Output Condition
Effects on Flag
When CSIE0 = 1, CSIIF0 set (rising Timing of signal output
execution of
edge of 9th clock
instruction for
of SCK0)
9
10
data write to SIO0
(serial transfer
start instruction)
Note 2
8
8
8
Meaning of Signal
to serial data bus
Note 1
Address value of slave
device on the serial bus
Instruction messages to
the slave device
Numeric values to be
processed with slave
or master device
Advertisement
Table of Contents
