NEC 78014Y Series User Manual page 276

(4) Interrupt timing specification register (SINT)
This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level
status.
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SINT to 00H.
Symbol 7
SINT 0
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Notes 1. Bit 6 (CLD) is a Read-Only bit.
2. When using wake-up function, set SIC to 0.
3. When CSIE0 = 0, CLD becomes 0.
Caution Be sure to set bit 0 to bit 3 to 0.
Remark SVA
CSIIF0: Interrupt request flag supports the INTCSI0
CSIE0 : Bit 7 of the serial operating mode register 0 (CSIM0)
276
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries)
Figure 15-7. Interrupt Timing Specification Register Format
<6> <5> <4> 3
CLD SIC SVAM 0
: Slave address register
2 1 0 Address
0 0 0 FF63H
R/W
SVAM
0
1
R/W
SIC
0
1
R
CLD
0
1
When Reset R/W
Note 1
00H R/W
SVA Bit to be Used as Slave Address
Bit 0 to Bit 7
Bit 1 to Bit 7
INTCSI0 Interrupt Factor Selection
CSIIF0 is set (1) upon termination of serial
channel 0 transfer
CSIIF0 is set (1) upon bus release
detection termination of serial interface
channel
Note 3
SCK0/P27 Pin Level
Low Level
High Level
Note 2