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2
(1) I
C bus mode functions
In the I
(a) Automatic identification of serial data
(b) Chip selection by specifying device addresses
(c) Wake-up function
(d) Acknowledge signal (ACK) control function
(e) Wait signal (WAIT) control function
2
(2) I
C bus definition
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This section describes the format of serial data communications and functions of the signals used in the I
mode.
The transfer timings of the start condition, data, and stop condition signals, which are output onto the signal data
bus of the I
SDA0 (SDA1)
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
2
C bus mode, the following functions are available.
Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in
series through the serial data bus.
The master device can select a specific slave device connected to the I
sending in advance the address data corresponding to the destination device.
Interrupt request occurs only if the received address equal to the value of the slave address register (SVA)
during slave operation. Therefore, CPUs other than the selected slave device on the I
independent operations during the serial communication.
The master device and a slave device send and receive acknowledge signals to confirm that the serial
communication has been executed normally.
The slave device controls a wait signal on the bus to inform the master device of the wait status.
2
C bus, are shown in Figure 16-37.
Figure 16-37. I
SCL
1 to 7
Start
Address
condition
2
C Bus Serial Data Transfer Timing
8
9
1 to 7
8
R/W ACK
Data
2
C bus and communicate with it by
9
1 to 7
8
9
ACK
Data
ACK
2
C bus can perform
2
C bus
Stop
condition
379
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