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SB0 (SB1)
ACKD
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SB0 (SB1)
SB0 (SB1)
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries)
(a) When ACK signal is output at 9th clock of SCK0
SIO0
SCK0
6
SB0 (SB1)
D2
ACKD
(b) When ACK signal is output after 9th clock of SCK0
SIO0
SCK0
6
7
D2
D1
(c) Clear timing when transfer start is instructed in BUSY
SIO0
SCK0
6
7
D2
D1
ACKD
SCK0
6
7
D2
D1
BSYE
Figure 15-25. ACKD Operations
7
8
9
D1
D0
ACK
8
9
D0
8
9
D0
Figure 15-26. BSYE Operation
8
9
D0
When BSYE = 1 at this point
Transfer Start Instruction
Transfer Start
Transfer Start Instruction
ACK
Transfer Start Instruction
ACK
BUSY
ACK
BUSY
Reset is performed during this
period, and SB0 (SB1) changes
when BSYE is 0 at the falling
edge of SCK0.
Transfer Start
D7
D6
299
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