NEC 78014Y Series User Manual page 388

(c) Interrupt timing specification register (SINT)
SINT is set by the 1-bit or 8-bit memory manipulation instruction.
RESET input sets SINT to 00H.
Symbol 7
SINT 0
R/W WAT1 WAT0
0
0
1
1
R/W WREL
0
1
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R/W CLC
0
1
Notes 1. Bit 6 (CLD) is Read-Only bit.
2. When the I
388
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
<6> <5> <4> <3>
CLD SIC SVAM CLC
Wait and Interrupt Control
0 Generates interrupt service request at rising edge of 8th SCK0 clock cycle. (Keeping clock output
in high impedance)
1 Setting prohibited
0 Used in the I 2 C bus mode (8-clock wait)
Generates interrupt service request at rising edge of 8th SCL clock cycle. (In the case of master
device, makes SCL output low to enter wait state after output. In the case of slave device, makes
SCL output low to request wait pulses are input.)
2
1 Used in the I C bus mode. (9-clock wait)
Generates interrupt service request at rising edge of 9th SCL clock cycle. (In the case of master
device, makes SCL output low to enter wait state after output. In the case of slave device, makes
SCL output low to request waits pulses are input.)
Wait State Cancellation Control
Wait state has been cancelled.
Cancels wait state.
Automatically cleared to 0 when the state is cancelled.
(Used to cancel wait state by means of WAT0 and WAT1.)
Clock Level Control
2
Used in the I C bus mode.
Make output level of SCL pin low unless serial transfer is being performed.
2
Used in I C bus mode.
Make SCL pin enter high-impedance state unless serial transfer is being performed (except for clock line
which is kept high)
Use to enable master device to generate start condition and stop condition signal.
2
C bus mode is used, be sure to set 1 and 0, or 1 and 1 in WAT0 and WAT1, respectively.
<2> 1 0 Address
WREL WAT1 WAT0 FF63H
Note 2
When Reset R/W
Note 1
00H R/W
(continued)