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Symbol
<7>
ADM
CS
ADM3 ADM2 ADM1
0
0
0
0
1
1
1
1
FR1
0
0
1
1
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TRG
0
1
CS
0
1
Set so that the A/D conversion time is 19.1 µ s or more.
Notes
1.
Setting prohibited because A/D conversion time is less than 19.1 µ s.
2.
Cautions 1. Set bit 0 to 1.
2. To reduce power dissipation in the A/D converter when standby functions used, the bit 7 (CS)
3. To restart the stopped A/D conversion operation, the interrupt request flag (ADIF) should be
Remark
f
: Main system clock oscillation frequency
X
252
CHAPTER 14 A/D CONVERTER
Figure 14-2. A/D Converter Mode Register Format
<6>
5
4
3
TRG
FR1
FR0
ADM3 ADM2 ADM1
Analog Input Channel Selection
0
0
ANI0
0
1
ANI1
1
0
ANI2
1
1
ANI3
0
0
ANI4
0
1
ANI5
1
0
ANI6
1
1
ANI7
FR0
A/D Conversion Time Selection
0
160/f
X
1
80/f
X
0
200/f
X
1
Setting prohibited
External Trigger Selection
No external trigger (software starts mode)
Conversion started by external trigger (hardware starts mode)
A/D Conversion Operation Control
Operation stop
Operation start
should be cleared to 0 to stop the A/D conversion operation before executing a HALT or STOP
instruction.
cleared to 0 before starting the A/D conversion operation.
2
1
0
Address
1
FF80H
Note 1
When operated at
When operated at
f
= 10.0 MHz
f
= 8.38 MHz
X
X
19.1 µ s
Note 2
Setting prohibited
Setting prohibited
Note 2
Setting prohibited
20.0 µ s
23.9 µ s
When Reset
R/W
01H
R/W
When operated at
f
= 4.19 MHz
X
38.1 µ s
19.1 µ s
Note 2
47.7 µ s
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