Table of Contents
Advertisement
(f) Busy signal (BUSY), Ready signal (READY)
www.DataSheet4U.com
(3) Register setting
The SBI mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register
(SBIC) and the interrupt timing specification register (SINT).
(a) Serial operating mode register 0 (CSIM0)
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries)
The busy signal informs the master that the slave is busy transmitting/receiving data.
The ready signal informs the master that the slave is ready to transmit/receive data.
Figure 15-20. Busy Signal and Ready Signal
SB0 (SB1)
Remark The broken line indicates the READY state.
In the SBI mode, the slave informs the master of the busy state by setting the SB0 (SB1) line to low level.
The busy signal is output following the acknowledge signal output by the slave. The busy signal is set/cleared
synchronously with the falling edge of SCK0. The master terminates automatically to output the serial clock
SCK0 when the busy signal is cleared.
The master can start subsequent transmissions when the busy signal is cleared and changes to the ready
state.
Caution In the SBI mode, the BUSY signal is output until the falling of the next serial clock after
the BUSY release indication. If WUP = 1 is set by mistake during this period, BUSY will
not be released. Thus, after releasing BUSY, be sure to check that the SB0 (SB1) has
become high level before setting WUP = 1.
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM0 to 00H.
SCK0
8
9
ACK
BUSY
READY
291
Advertisement
Table of Contents
