Clock Generator Operations - NEC 78014Y Series User Manual

7.5 Clock Generator Operations

The clock generator generates the following types of clocks and controls the CPU operating mode including the
standby mode.
• Main system clock f
• Subsystem clock f
• CPU clock f
• Clock to peripheral hardware
The function and operation of the clock generator circuit are determined by the processor clock control register
(PCC) as follows:
(a) Upon generation of the RESET signal, the lowest speed mode of the main system clock (6.4 µ s when operated
at 10.0 MHz) is selected (PCC = 04H). Main system clock oscillation stops while low level is applied to the RESET
pin.
(b) With the main system clock selected, one of the five (0.4 µ s, 0.8 µ s, 1.6 µ s, 3.2 µ s and 6.4 µ s: when operated
at 10.0 MHz) CPU clock stages can be selected by setting the PCC.
(c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. With the
subsystem clock unused, the current consumption in STOP mode can be further decreased by disabling the
subsystem clock feedback resistor with PCC bit 6 (FRC).
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(d) The PCC can be used to select the subsystem clock and to operate the system with low current consumption
(122 µ s at 32.768 kHz operation).
(e) With the subsystem clock selected, main system clock oscillation can be stopped with the PCC. The HALT mode
can be used. However, the STOP mode cannot be used. (Subsystem clock oscillation cannot be stopped.)
(f) The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied to
the watch timer and clock output functions only. Thus, the watch function and the clock output function can also
be continued in the standby state. However, since all other peripheral hardware operate with the main system
clock, the peripheral hardware also stops if the main system clock is stopped (except external input clock
operation).
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CHAPTER 7 CLOCK GENERATOR
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