Interrupt Request Reserve - NEC 78014Y Series User Manual

18.4.5 Interrupt request reserve

Some instructions may reserve the acknowledge of an instruction request until the completion of the execution
of the next instruction even if the interrupt request is generated during the execution. The following shows such
instructions (interrupt request reserve instruction).
• MOV PSW, #byte
• MOV A, PSW
• MOV PSW, A
• MOV1 PSW.bit, CY
• MOV1 CY, PSW.bit
• AND1 CY, PSW.bit
• OR1 CY, PSW.bit
• XOR1 CY, PSW.bit
• SET1 PSW.bit
• CLR1 PSW.bit
• RETB
• RETI
• PUSH PSW
• POP PSW
• BT PSW.bit, $addr16
• BF PSW.bit, $addr16
• BTCLR PSW.bit, $addr16
• EI
• DI
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• Manipulation instructions for IF0L, IF0H, MK0L, MK0H, PR0L, PR0H and INTM0 registers
Caution BRK instruction is not an interrupt request reserve instruction described above. However, in a
software interrupt started by the execution of BRK instruction, the IE flag is cleared to 0.
Therefore, interrupt requests are not acknowledged even when a maskable interrupt request is
issued during the execution of the BRK instruction. However, non-maskable interrupt requests
are acknowledged.
Figure 18-16 shows the interrupt request reserve timing.
CPU Processing
××
IF
Remarks 1. Instruction N : Interrupt request reserve instruction
2. Instruction M : Instruction except interrupt reserve instructions
3. Operation of ××IF (interrupt request) is not affected by ××PR (priority level) value.
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CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION
Figure 18-16. Interrupt Request Reserve
Instruction N Instruction M
PSW, PC Save, Jump to Interrupt Servicing
Interrupt Servicing Program