SP←SP–2
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SP←SP+2
Figure 5-9. Data to be Saved to Stack Memory
PUSH rp Instruction
↑
Register Pair Lower
SP–2
↑
SP–1
Register Pair Upper
↑
SP→
Figure 5-10. Data to be Reset from Stack Memory
POP rp Instruction
SP→
Register Pair Lower
↓
SP+1
Register Pair Upper
↓
CHAPTER 5 CPU ARCHITECTURE
CALL, CALLF, and
CALLT Instruction
SP←SP–2
↑
PC7 to PC0
SP–2
↑
SP–1
PC15 to PC8
↑
SP →
RET Instruction
SP→
PC7 to PC0
↓
SP+1
PC15 to PC8
↓
SP←SP+2
Interrupt and
BRK Instruction
SP←SP–3
↑
SP–3
PC7 to PC0
↑
SP–2
PC15 to PC8
↑
SP–1
PSW
↑
SP →
RETI and RETB
Instruction
SP→
PC7 to PC0
↓
SP+1
PC15 to PC8
↓
SP+2
PSW
↓
SP←SP+3
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