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Symbol
TCL3
TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30
TCL33 TCL32 TCL31 TCL30
TCL37 TCL36 TCL35 TCL34
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Note
Can be set only when the main system clock oscillate at 4.19 MHz or less.
Caution
Remarks 1.
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
Figure 16-5. Timer Clock Select Register 3 Format
7
6
5
4
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
Other than above
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
Other than above
If TCL3 is to be rewritten in data other than identical data, the serial transfer must be stopped first.
f
: Main system clock oscillation frequency
X
2.
Value in parentheses apply to operation with f
3
2
1
0
Serial Interface Channel 0 Serial Clock Seletion
Serial Clock in I
2
C bus mode
6
f
/2
(156 kHz)
X
f
/2
7
(78.1 kHz)
X
f
/2
8
(39.1 kHz)
X
9
f
/2
(19.5 kHz)
X
f
/2
10
(9.8 kHz)
X
11
f
/2
(4.9 kHz)
X
12
f
/2
(2.4 kHz)
X
f
/2
13
(1.2 kHz)
X
Setting prohibited
Serial Interface Channel 1 Serial Clock Seletion
f
/2
2 Note
X
3
f
/2
(1.25 MHz)
X
f
/2
4
(625 kHz)
X
f
/2
5
(313 kHz)
X
6
f
/2
(156 kHz)
X
f
/2
7
(78.1 kHz)
X
8
f
/2
(39.1 kHz)
X
9
f
/2
(19.5 kHz)
X
Setting prohibited
= 10.0 MHz.
X
Address
When Reset
R/W
FF43H
88H
R/W
Serial Clock in 3-wire/SBI/2-wire mode
2 Note
f
/2
X
f
/2
3
(1.25 MHz)
X
f
/2
4
(625 kHz)
X
5
f
/2
(313 kHz)
X
f
/2
6
(156 kHz)
X
7
f
/2
(78.1 kHz)
X
8
f
/2
(39.1 kHz)
X
f
/2
9
(19.5 kHz)
X
331
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