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(a) Bus release signal (REL)
The bus release signal is generated when the SCK0 line is in high level (a serial clock is not output) and
the SB0 (SB1) line changes from low level to high level.
The bus release signal is output by the master.
The bus release signal indicates the master will send the address to the slave. The slave contains hardware
to detect the bus release signal.
Caution The bus release signal is acknowledged when the SCK0 line is in high level, and the SB0
(b) Command Signal (CMD)
The command signal is generated when the SCK0 line is in high level (a serial clock is not output) and the
SB0 (SB1) line changes from high level to low level. The command signal is output by the master.
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The command signal indicates that master will send the command to the slave (However, the command signal
following the bus release signal indicates that address will be sent).
The slave contains hardware to detect the command signal.
Caution The command signal is acknowledged when the SCK0 line is in high level, and the SB0
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
Figure 16-14. Bus Release Signal
SCK0
SB0 (SB1)
(SB1) line changes from low level to high level. Thus, if the timing at which bus changes
deviates due to effects such as board capacity, it may be determined as the bus release
signal even if data is sent. Therefore perform wiring carefully.
Figure 16-15. Command Signal
SCK0
SB0 (SB1)
(SB1) line changes from high level to low level. Thus, if the timing at which bus changes
deviates due to effects such as board capacity, it may be determined as the command
signal even if data is sent. Therefore perform wiring carefully.
"H"
"H"
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