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Symbol
TMC0
TMC03 TMC02 TMC01 Operating Mode & Clear
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Cautions 1. Switch the clear mode and the TO0 output timing after stopping the timer operation (by setting
Remarks 1. TO0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER
Figure 8-5. 16-Bit Timer Mode Control Register Format
7
6
5
4
0
0
0
0
OVF0
16-Bit Timer Register Overflow Detection
0
Overflow not detected
1
Overflow detected
Mode Selection
0
0
0
Operation stop
(TM0 cleared to 0)
0
0
1
PWM mode
(free running)
0
1
0
Free running mode
0
1
1
1
0
0
Clear & start on TI0 valid
edge
1
0
1
1
1
0
Clear & start on match
between TM0 and CR00
1
1
1
TMC01 through TMC03 to 0, 0, 0).
2. Set the valid edge of the INTP0/P00/TI0 pin with an external interrupt mode register (INTM0)
and select the sampling clock frequency with a sampling clock select register (SCS).
3. When using the PWM mode, set the PWM mode and then set data to CR00.
4. If clear & start mode on match between TM0 and CR00 is selected, OVF0 flag is set to 1 when
the set value of CR00 is FFFFH and the value of TM0 changes from FFFFH to 0000H.
:
16-bit timer/event counter output pin
2. TI0
:
16-bit timer/event counter input pin
3. TM0
:
16-bit timer register
4. CR00 :
16-bit compare register
3
2
1
<0>
TMC03 TMC02 TMC01 OVF0
TO0 Output Timing
Selection
No change
PWM pulse output
Match between TM0 and
CR00
Match between TM0 and
CR00 or TI0 valid edge
Match between TM0 and
CR00
Match between TM0 and
CR00 or TI0 valid edge
Match between TM0 and
CR00
Match between TM0 and
CR00 or TI0 valid edge
Address
When Reset
R/W
FF48H
00H
R/W
Interrupt Request
Generation
Not generated
Generated on match
between TM0 and CR00
181
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