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R/W
R
R/W
CSIE0
Notes
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
WUP
Wake-up Function Control
0
Interrupt request signal generation with each serial transfer in all modes
1
Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1
when the SBI mode is used or when CMDD = 1 when the I
register (SVA) data in the SBI mode and the I
COI
Slave Address Comparison Result Flag
0
Slave address register (SVA) not equal to serial I/O shift register 0 (SIC0) data
1
Slave address register (SVA) equal to serial I/O shift register 0 (SIC0) data
Serial Interface Channel 0 Operation Control
0
Operation stopped
1
Operation enable
1. When the wake-up function is used, set bit 5 of the interrupt timing specification register (SINT) to 0.
Do not write data to serial I/O shift register 0 (SIO0) during WUP = 1.
2. When CSIE0 = 0, COI is 0.
Note 1
2
C bus mode
Note 2
2
C bus mode is used) matches the slave address
385
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