NEC 78014Y Series User Manual page 386

8-bit single-chip microcontrollers
Table of Contents

Advertisement

(b) Serial bus interface control register (SBIC)
SBIC is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SBIC to 00H.
Symbol
<7>
SBIC
BSYE ACKD ACKE
R/W
RELT
R/W
CMDT
R
RELD
Clear Conditions (RELD = 0)
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in address
reception
• When CSIE0 = 0
• When RESET input is applied
www.DataSheet4U.com
R
CMDD
Clear Conditions (CMDD = 0)
• When transfer start instruction is executed
• When stop condition is detected in the I
• When CSIE0 = 0
• When RESET input is applied
R/W
ACKT
Note
Bits 2, 3, and 6 (RELD, CMDD, ACKD) are Read-Only bits.
Caution
Be sure to set bit 7 to 0 when the I
Remark
CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
386
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
<6>
<5>
<4>
<3>
ACKT CMDD RELD CMDT
Use for stop condition output when the I
When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
Use for start condition output when the I
When CMDT = 1, SO latch is cleared to 0. After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
Stop Condition Detection
Start Condition Detection
When the I
2
C bus mode is used, SDA0 (SDA1) is made low-level until the next SCL falling edge
immediately after execution of the set instruction (ACKT = 1).
Used to generate ACK signal by software when 8-clock wait is selected.
Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
<2>
<1>
<0>
Address
RELT
FF61H
2
C mode is used.
2
C mode is used.
Set Conditions (RELD = 1)
• When stop condition is detected in the I
Set Conditions (CMDD = 1)
• When start condition is detected in the I
2
C bus mode
2
C bus is used.
When Reset
R/W
Note
00H
R/W
2
C bus mode
2
C bus mode
(continued)

Advertisement

Table of Contents
loading

Table of Contents