2.1 Features
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On-chip large-capacity ROM and RAM
Part
Number
µ PD78011BY
µ PD78012BY
µ PD78013Y
µ PD78014Y
µ PD78P014Y
Notes 1. 8, 16, 24, or 32 Kbytes can be selected by memory size switching register (IMS).
2. 512 or 1024 bytes can be selected by IMS.
•
External memory expanded space: 64 Kbytes
Minimum instruction execution time changeable from high speed (0.4 µ s: @ 10 MHz with main system clock)
•
to ultra-low speed (122 µ s: @ 32.768 kHz with subsystem clock)
•
Instruction set suitable for system control
• Bit manipulation enable in all the address space
• Multiplication/division instruction
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•
53 I/O ports (N-ch open-drain: 4)
•
8-bit resolution A/D converter: 8 channels
• Low-voltage operation (AV
•
Serial interface: 2 channels
• 3-wire serial I/O, SBI, 2-wire serial I/O, I
• 3-wire serial I/O mode (Automatic transmit/receive function): 1 channel
•
Timer: 5 channels
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter
• Watch timer
• Watchdog timer
•
14 vectored interrupt sources
•
2 test inputs
•
2 types of on-chip clock oscillator (main system clock and subsystem clock)
•
Power supply voltage: V
CHAPTER 2 OUTLINE ( µ PD78014Y Subseries)
CHAPTER 2 OUTLINE ( µ PD78014Y Subseries)
Item
Program Memory
(ROM)
8 Kbytes
16 Kbytes
24 Kbytes
32 Kbytes
Note 1
32 Kbytes
= 2.7 to 6.0 V: operable at the same supply voltage range as CPU)
DD
: 2 channels
: 1 channel
: 1 channel
= 2.7 to 6.0 V
DD
Data Memory
Internal high-speed RAM
512 bytes
1024 bytes
Note 2
1024 bytes
2
C bus mode: 1 channel
Buffer RAM
32 bytes
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