Cautions On Use Of I C Bus Mode - NEC 78014Y Series User Manual

16.4.6 Cautions on use of I
(1) Start condition output (master)
The SCL pin normally outputs the low-level signal when no serial clock is output. It is necessary to change the
SCL pin to high in order to output a start condition signal. Set 1 in bit 3 (CLC) of the interrupt timing specification
register (SINT) to drive the SCL pin high.
After setting CLC, clear CLC to 0 and return the SCL pin to low. If CLC remains 1, no serial clock is output.
If it is the master device which outputs the start condition and stop condition signals, confirm that CLD is set to
1 after setting CLC to 1. This is because a slave device may have set SCL to low (wait state).
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
2
C bus mode
Figure 16-47. Start Condition Output
SCL
SDA0 (SDA1)
CLC
CMDT
CLD