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20.2 Standby Function Operations
20.2.1 HALT mode
(1) HALT mode set and operating status
The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the
subsystem clock.
The operating status in the HALT mode is described below.
Item
Clock generator
CPU
Port (output latch)
16-bit timer/event counter
8-bit timer/event counter
Watchdog timer
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A/D converter
Watch timer
Serial
Interface
External
interrupt
Bus line in AD0 to AD7
External
Expansion ASTB
Notes
Table 20-1. HALT Mode Operating Status
HALT Mode
When HALT instruction is executed during
Setting
main system clock oscillation
Without subsystem
clock
Note 1
Both main system clock and subsystem clock can be oscillated.
Clock supply to the CPU stops.
Operation stop.
Status before HALT instruction execution is held.
Operation enabled.
Operation enabled.
Operation enabled.
Operation enabled.
Operation enabled
when f
/2
8
X
for the count clock.
Other than auto- Operation enabled.
matic transmit/
receive function
Automatic
Operation stop.
transmit/receive
function
INTP0
Operation enabled when the clock (f
hardware are selected as sampling clock.
INTP1 to INTP3 Operation enabled.
High-impedance
A8 to A15
Status before HALT instruction execution is held.
Low level
WR, RD
High level
WAIT
High-impedance
1.
Includes case when an external clock is not supplied in the subsystem clock.
2.
Includes case when an external clock is supplied in the subsystem clock.
CHAPTER 20 STANDBY FUNCTION
With subsystem
clock
Note 2
Operation enabled.
is selected
/2
6
and f
X
When HALT instruction is executed during
subsystem clock oscillation
When main system
When main system
clock oscillation continues
clock oscillaton stops
Operation stop.
Operation enabled
when TI1 and TI2 are
selected for the count
clock.
Operation stop.
Operation stop.
Operation enabled
when f
for the count clock.
Operation enabled
when external SCK is
selected.
/2
7
) for the peripheral
Operation stop.
X
is selected
XT
485
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