7.3 Clock Generator Control Register
The clock generator is controlled by the processor clock control register (PCC). The PCC sets CPU clock selection,
the ratio of division, main system clock oscillator operation/stop and subsystem clock oscillator on-chip feedback
resistor enable/disable.
The PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the PCC to 04H.
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CHAPTER 7 CLOCK GENERATOR
Figure 7-2. Feedback Resistor of Subsystem Clock
FRC
P-ch
Feedback resistor
XT1
XT2
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