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(c) Interrupt timing specification register (SINT)
Symbol
SINT
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Notes
Caution
Remark
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 ( µ PD78014 Subseries)
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SINT to 00H.
7
<6>
<5>
<4>
0
CLD
SIC
SVAM
1. Bit 6 (CLD) is a Read-Only bit.
2. When using wake-up function, set SIC to 0.
3. When CSIE0 = 0, CLD becomes 0.
Be sure to set bits 0 to 3 to 0.
SVA
: Slave address register
CSIIF0: Interrupt request flag supports the INTCSI0
CSIE0 : Bit 7 of the serial operating mode register 0 (CSIM0)
3
2
1
0
0
0
0
0
R/W
SVAM
R/W
R
Address
When Reset
R/W
FF63H
00H
R/W
SVA Bit to be Used as Slave Address
0
Bits 0 to 7
1
Bits 1 to 7
SIC
INTCSI0 Interrupt Factor Selection
0
CSIIF0 is set (1) upon termination of serial
channel 0 transfer
1
CSIIF0 is set (1) upon bus release
detection
CLD
SCK0/P27 Pin Level
Note 3
0
Low Level
1
High Level
Note 1
Note 2
295
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