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(c) Interrupt timing specification register (SINT)
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SINT to 00H.
Symbol
7
SINT
0
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Notes
1. Bit 6 (CLD) is a Read-Only bit.
2. When using wake-up function, set SIC to 0.
3. When CSIE0 = 0, CLD becomes 0.
Caution
Be sure to set bits 0 to 3 to 0 when the SBI mode is used.
Remark SVA
CSIIF0 : Interrupt request flag supports the INTCSI0
CSIE0 : Bit 7 of the serial operating mode register 0 (CSIM0)
356
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
<6>
<5>
<4>
<3>
CLD
SIC
SVAM
CLC
: Slave address register
<2>
1
0
Address
WREL WAT1 WAT0
FF63H
R/W
SVAM
0
1
R/W
SIC
0
1
R
CLD
0
1
When Reset
R/W
Note 1
00H
R/W
SVA Bit to be Used as Slave Address
Bits 0 to 7
Bits 1 to 7
INTCSI0 Interrupt Factor Selection
CSIIF0 is set (1) upon termination of serial
channel 0 transfer
CSIIF0 is set (1) upon bus release
detection in SBI mode.
Note 3
SCK0/SCL/P27 Pin Level
Low Level
High Level
Note 2
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