NEC 78014Y Series User Manual page 390

(4) Various signals
A list of signals in the I
Signal name Signaled by
Start condition Master
Stop condition Master
Acknowledge Master or
signal (ACK) slave
Wait (WAIT) Slave
Serial Clock Master
(SCL)
Address Master
(A6 to A0)
Transfer Master
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direction
(R/W)
Data Master or
(D7 to D0) slave
Notes 1. The level of the serial clock can be controlled by bit 3 (CLC) of the interrupt timing specification register
(SINT).
2. In the wait state, the serial transfer operation will be started after the wait state is released.
3. If the 8-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 8th clock cycle of
SCL. If the 9-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 9th clock cycle
of SCL.
If WUP = 1, CSIIF0 is set only when an address is received and the address matches the slave address
register (SVA) value.
390
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78014Y Subseries)
2
C bus mode is given in Table 16-6.
Table 16-6. Signals in the I
Definition
SDA0 (SDA1) falling edge
when SCL is high Note 1
SDA0 (SDA1) rising edge
when SCL is high Note 1
Low level of SDA0 (SDA1)
pin during one SCL clock
cycle after serial reception
Low-level signal output
to SCL
Synchronization clock for
output of various signals
7-bit data synchronized with
SCL immediately after start
condition signal
1-bit data output in synchro- serial transfer
nization with SCL after
address output
8-bit data synchronized with
SCL, not immediately after
start condition
2
C Bus Mode
Signaled when Affected flag(s)
CMDT is set. CMDD is set.
RELT is set. RELD is set and
CMDD is cleared
• ACKE = 1. ACKD is set.
• ACKT is set.
WAT1, —
WAT0 = 1×.
Execution of data CSIIF0 is
write instruction set. Note 3
to SIO0 when
CSIE0 = 1
(instruction of
start) Note 2
Function
Indicates that serial
communication starts and
subsequent data are
address data.
Indicates end of serial
transmission.
Indicates completion of
reception of 1 byte.
Indicates state in which
serial reception is not
possible.
Serial communication
synchronization signal.
Indicates address value
for specification of slave
on serial bus.
Indicates whether data
transmission or reception
is to be performed.
Contains data actually to
be sent.