Table of Contents
Advertisement
Instruc- Mnemonic
tion
Group
Condi-
tional
Branch
CPU
Control NOP
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
www.DataSheet4U.com
Operands
DBNZ
B, $addr16
C, $addr16
saddr, $addr16
SEL
RBn
EI
DI
HALT
STOP
register (PCC).
2. Clock indicates when a program is in the internal ROM area.
CHAPTER 23 INSTRUCTION SET
Byte
Clock
Note 1
Note 2
2
12
—
2
12
—
3
16
20
2
8
—
1
4
—
2
—
12
2
—
12
2
12
—
2
12
—
Operation
B ← B–1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C–1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
(saddr) ← (saddr) – 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
RBS1, 0 ← n
No Operation
IE ← 1 (Enable Interrupt)
IE ← 0 (Disable Interrupt)
Set HALT Mode
Set STOP Mode
) selected by processor clock control
CPU
Flag
Z
AC CY
515
Advertisement
Table of Contents
