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(a) In case the automatic data transmit/receive function is performed by an internal clock
When bit 1 (CSIM11) of the serial operation mode register 1 (CSIM1) is set to 1, the internal clock performs.
In this case, the interval is determined as follows by CPU processing.
Figure 17-23. Operating Timing in Operating Automatic Transmission/Reception
T
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f
CPU
(n = 1)
SCK1
SO1
SI1
f
: CPU clock (set by bit 0 to bit 2 (PCC0 to PCC2) of processor clock control register (PCC))
CPU
T
: 1/f
CPU
T
: 1/f
SCK
f
: Serial clock frequency
SCK
444
CHAPTER 17 SERIAL INTERFACE CHANNEL 1
Table 17-2. Interval by CPU Processing (in Internal Clock Operation)
CPU Processing
When using multiply instruction
When using divide instruction
External access 1 wait mode
Other than above
T
: 1/f
SCK
SCK
f
: Serial clock frequency
SCK
T
: 1/f
CPU
CPU
f
: CPU clock (set by bit 0 to bit 2 (PCC0 to PCC2) of processor clock control
CPU
register)
MAX. (a, b) : a or b, whichever greater
with Internal Clock
CPU
T
SCK
D7
D6
D5
D7
D6
D5
CPU
SCK
Interval
MAX. (2.5 T
SCK
MAX. (2.5 T
SCK
MAX. (2.5 T
SCK
MAX. (2.5 T
SCK
D4
D3
D2
D4
D3
D2
, 26 T
)
CPU
, 40 T
)
CPU
, 18 T
)
CPU
, 14 T
)
CPU
Interval
D1
D0
D1
D0
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